This invention relates to integrated circuits and, more particularly, to integrated circuits which include an optical semiconductor device integrally formed with a photo diode and a bipolar IC.
A monolithic optical semiconductor device is formed integrally with a light receiving element and a peripheral circuit with a hybrid IC combined with a separately produced light receiving element and other circuit elements. It has been found that such a monolithic optical semiconductor device is produced at a lower cost than similar elements built up from discrete components, and is relatively free from noise caused by external electromagnetic fields.
Referring to FIG. 9, a light receiving element of a conventional optical semiconductor device is disclosed in, for example, Japanese Laid-open Patent Publication 61-47664. The conventional optical semiconductor device includes an N-type epitaxial layer 2 formed on a P-type substrate 1. A plurality of N-type island areas 4 are isolated from each other by P.sup.+ -type isolating areas 3 therebetween. A photo diode 7 is formed in an upper surface of one of the illustrated N-type island areas by a PN junction between a P.sup.- type diffusion area 5 and an N.sup.+ -type diffusion area 6. An N.sup.+ -type buried layer 8 spans the interface between N-type area 4 and P-type substrate 1.
A companion NPN transistor 9, in its own N-type island area 4, includes an N.sup.+ -type buried layer 8 spanning the interface between N-type area 4 and P-type substrate 1. An n-type well area 10 is formed in N-type island area 4. A P-type base area 40 is formed in the upper surface of N-type well area 10. An N.sup.+ -type emitter area 41 is disposed in the upper surface of P-type base area 40. An N.sup.+ -type collector contact area 41 is disposed in the upper surface of N-type well area 10.
To obtain improved performance from photo diode 7, the resistivity of its island area 4, which will be a cathode, is preferably made as large as possible, in order to reduce the capacitance of the device. However, when N-type epitaxial layer 2 is grown on P-type substrate 1, impurities tend to migrate from P-type substrate 1, or from external sources, into N-type epitaxial layer 2. The impurities are mainly P-type impurities derived from boron auto doping. Therefore, when doping for high resistivity in N-type epitaxial layer 2, the migration of P-type impurities into N-type epitaxial layer 2 makes it difficult to ensure that N-type epitaxial layer 2 actually remains N-type, instead of being converted to P-type by the impurities. The incorporation of N-type well area 10 in the N-type island area 4 of NPN transistor 9 tends to compensate for the concentration of P-type impurites in this area. As a result, lower resistivity is attainable for improved performance of photo diode 7.
Nevertheless, the problem of excessive P-type impurities still limits the amount by which resistance value and conductivity can be controlled.
Because high resistivity is not available, it is impossible to increase the width of the depletion layer forming the PN junction of photo diode 7. Therefore it is impossible to reduce the junction capacitance, which determines the properties of photo diode 7, as much as would otherwise be possible.
A further disadvantage of this prior-art device is that the response speed of photo diode 7 is degraded by the relatively long transit time of carriers originating outside the depletion layer in the depth of P-type diffusion area 5 or epitaxial layer 2.